#--------------------------
# timing and area
#--------------------------

set_max_area 0

set top_clk         "clk"
set clk_period      "8"

create_clock -p $clk_period [get_ports $top_clk]
set_dont_touch_network [get_clocks $top_clk]
set_clock_uncertainty 0.5 [get_clocks $top_clk]

set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $top_clk]]

set_input_delay [expr $clk_period * 0.6] -clock $top_clk $all_in_ex_clk 
set_output_delay -max [expr $clk_period * 0.6] -clock $top_clk [all_outputs]

#-----------------------------
# set operating environment
#-----------------------------
set_operating_conditions typical
set_wire_load_model -name smic18_wl10
set auto_wire_load_selection false
set_wire_load_mode top

set_driving_cell -library typical -lib_cell NAND2X1 -pin Y $all_in_ex_clk
set_load [expr [load_of typical/NAND2X1/A] * 3 ] [all_outputs]

